Our heuristic seeks not only to reduce the number of configurations that must be examined, but also traverses the search space in a way that minimizes costly cache flushes. We propose to move that CAD on-chip, which can greatly increase the acceptance of tunable caches.We introduce on-chip hardware implementing an efficient cache tuning heuristic that can automatically, transparently, and dynamically tune the cache to an executing program.

Tuning those caches to a program is still, however, a cumbersome task left for designers, assisted in part by recent computer-aided design (CAD) tuning aids. However, several configurable cache architectures have been proposed recently for use in prefabricated microprocessor platforms. Customizing caches has until recently been restricted to core-based flows, in which a new chip will be fabricated. Customizing a microprocessor cache's total size, line size, and associativity to a particular program is well known to have tremendous benefits for performance and power. Memory accesses often account for about half of a microprocessor system's power consumption. To verify the reconfiguration process, a MicroBlaze-based embedded system is implemented, and reconfiguration is carried out via the Xilinx Internal Configuration Access Port (ICAP) and driver software. Our results show that the proposed approach can fit a classification circuit 4 times larger than an equivalent VRC-based approach, and 6 times larger than a shift register-based approach, in a Xilinx Virtex-5 device. For demonstration, we rely on a hardware signal classifier application. This allows for an easy and flexible architecture specification, as well as possible implementation improvements over a hand-placed design. We specify the goal architecture in VHDL and read out the locations of the automatically placed LUTs for use in an online reconfiguration setting. Neither manual placement nor any proprietary bitstream manipulation is required in the simplest form of the employed method.

In this paper, we show how fine-grained partial reconfiguration of 6-input LUTs of modern Xilinx FPGAs can lead to significantly more efficient resource utilization in an EHW application. In related work, virtual reconfigurable circuits (VRC), partial reconfiguration, and lookup table (LUT) reconfiguration approaches have been investigated. When applied on modern FPGAs, the technically challenging reconfiguration process becomes an issue and can be approached at multiple levels. The evolvable hardware (EHW) paradigm relies on continuous run-time reconfiguration of hardware.

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